circuit BetterBooth :
  module BetterBooth :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip x : UInt<16>, flip y : UInt<16>, busy : UInt<1>, flip start : UInt<1>, z : UInt<32>}

    reg yReg : UInt<19>, clock with :
      reset => (reset, UInt<19>("h0")) @[BetterBooth.scala 11:21]
    reg sumReg : SInt<32>, clock with :
      reset => (reset, asSInt(UInt<32>("h0"))) @[BetterBooth.scala 12:23]
    reg cnt : UInt<4>, clock with :
      reset => (reset, UInt<4>("h0")) @[BetterBooth.scala 13:20]
    reg state : UInt<2>, clock with :
      reset => (reset, UInt<2>("h0")) @[BetterBooth.scala 17:22]
    wire nextState : UInt<2> @[BetterBooth.scala 18:23]
    node _T = mux(io.start, UInt<2>("h1"), UInt<2>("h0")) @[BetterBooth.scala 20:21]
    node _T_1 = eq(cnt, UInt<4>("h8")) @[BetterBooth.scala 21:29]
    node _T_2 = mux(_T_1, UInt<2>("h2"), UInt<2>("h1")) @[BetterBooth.scala 21:24]
    node _nextState_T = eq(UInt<2>("h0"), state) @[Mux.scala 81:61]
    node _nextState_T_1 = mux(_nextState_T, _T, UInt<2>("h0")) @[Mux.scala 81:58]
    node _nextState_T_2 = eq(UInt<2>("h1"), state) @[Mux.scala 81:61]
    node _nextState_T_3 = mux(_nextState_T_2, _T_2, _nextState_T_1) @[Mux.scala 81:58]
    node _nextState_T_4 = eq(UInt<2>("h2"), state) @[Mux.scala 81:61]
    node _nextState_T_5 = mux(_nextState_T_4, UInt<2>("h0"), _nextState_T_3) @[Mux.scala 81:58]
    nextState <= _nextState_T_5 @[BetterBooth.scala 24:13]
    state <= nextState @[BetterBooth.scala 25:9]
    io.busy <= UInt<1>("h0") @[BetterBooth.scala 27:11]
    io.z <= UInt<1>("h0") @[BetterBooth.scala 28:8]
    reg xReg : SInt<32>, clock with :
      reset => (reset, asSInt(UInt<32>("h0"))) @[BetterBooth.scala 29:21]
    reg lastResultReg : UInt<32>, clock with :
      reset => (reset, UInt<32>("h0")) @[BetterBooth.scala 31:30]
    node _T_3 = eq(UInt<2>("h0"), state) @[BetterBooth.scala 49:17]
    when _T_3 : @[BetterBooth.scala 49:17]
      cnt <= UInt<1>("h0") @[BetterBooth.scala 51:11]
      wire _xReg_WIRE : SInt<16> @[BetterBooth.scala 52:28]
      node _xReg_T = asSInt(io.x) @[BetterBooth.scala 52:28]
      _xReg_WIRE <= _xReg_T @[BetterBooth.scala 52:28]
      xReg <= _xReg_WIRE @[BetterBooth.scala 52:12]
      io.z <= lastResultReg @[BetterBooth.scala 53:12]
      node _yReg_T = dshl(io.y, UInt<1>("h1")) @[BetterBooth.scala 54:21]
      wire _yReg_WIRE : SInt<16> @[BetterBooth.scala 54:55]
      node _yReg_T_1 = asSInt(io.y) @[BetterBooth.scala 54:55]
      _yReg_WIRE <= _yReg_T_1 @[BetterBooth.scala 54:55]
      node _yReg_T_2 = lt(_yReg_WIRE, asSInt(UInt<1>("h0"))) @[BetterBooth.scala 54:71]
      node _yReg_T_3 = dshl(UInt<19>("h3"), UInt<5>("h11")) @[BetterBooth.scala 54:101]
      node _yReg_T_4 = mux(_yReg_T_2, _yReg_T_3, UInt<1>("h0")) @[BetterBooth.scala 54:41]
      node _yReg_T_5 = add(_yReg_T, _yReg_T_4) @[BetterBooth.scala 54:36]
      node _yReg_T_6 = tail(_yReg_T_5, 1) @[BetterBooth.scala 54:36]
      yReg <= _yReg_T_6 @[BetterBooth.scala 54:12]
      sumReg <= asSInt(UInt<1>("h0")) @[BetterBooth.scala 55:14]
    else :
      node _T_4 = eq(UInt<2>("h1"), state) @[BetterBooth.scala 49:17]
      when _T_4 : @[BetterBooth.scala 49:17]
        node _T_5 = bits(yReg, 2, 0) @[BetterBooth.scala 33:22]
        lastResultReg <= UInt<1>("h0") @[BetterBooth.scala 59:21]
        node _T_6 = bits(yReg, 2, 0) @[BetterBooth.scala 33:22]
        node _T_7 = asUInt(xReg) @[BetterBooth.scala 66:14]
        node _T_8 = sub(asSInt(UInt<1>("h0")), xReg) @[BetterBooth.scala 67:10]
        node _T_9 = tail(_T_8, 1) @[BetterBooth.scala 67:10]
        node _T_10 = asSInt(_T_9) @[BetterBooth.scala 67:10]
        node _T_11 = asUInt(_T_10) @[BetterBooth.scala 67:17]
        node _T_12 = bits(reset, 0, 0) @[BetterBooth.scala 60:13]
        node _T_13 = eq(_T_12, UInt<1>("h0")) @[BetterBooth.scala 60:13]
        when _T_13 : @[BetterBooth.scala 60:13]
          printf(clock, UInt<1>("h1"), "[%d state=%b], yReg=%b, yRegLast=%b, x=%b, -x=%b\n", cnt, state, yReg, _T_6, _T_7, _T_11) : printf @[BetterBooth.scala 60:13]
        node _T_14 = bits(yReg, 2, 0) @[BetterBooth.scala 33:22]
        node _T_15 = dshl(xReg, UInt<1>("h1")) @[BetterBooth.scala 47:24]
        node _T_16 = dshl(xReg, UInt<1>("h1")) @[BetterBooth.scala 47:24]
        node _T_17 = sub(asSInt(UInt<1>("h0")), _T_16) @[BetterBooth.scala 77:25]
        node _T_18 = tail(_T_17, 1) @[BetterBooth.scala 77:25]
        node _T_19 = asSInt(_T_18) @[BetterBooth.scala 77:25]
        node _T_20 = sub(asSInt(UInt<1>("h0")), xReg) @[BetterBooth.scala 78:25]
        node _T_21 = tail(_T_20, 1) @[BetterBooth.scala 78:25]
        node _T_22 = asSInt(_T_21) @[BetterBooth.scala 78:25]
        node _T_23 = sub(asSInt(UInt<1>("h0")), xReg) @[BetterBooth.scala 79:25]
        node _T_24 = tail(_T_23, 1) @[BetterBooth.scala 79:25]
        node _T_25 = asSInt(_T_24) @[BetterBooth.scala 79:25]
        node _T_26 = eq(UInt<1>("h1"), _T_14) @[Mux.scala 81:61]
        node _T_27 = mux(_T_26, xReg, asSInt(UInt<1>("h0"))) @[Mux.scala 81:58]
        node _T_28 = eq(UInt<2>("h2"), _T_14) @[Mux.scala 81:61]
        node _T_29 = mux(_T_28, xReg, _T_27) @[Mux.scala 81:58]
        node _T_30 = eq(UInt<2>("h3"), _T_14) @[Mux.scala 81:61]
        node _T_31 = mux(_T_30, _T_15, _T_29) @[Mux.scala 81:58]
        node _T_32 = eq(UInt<3>("h4"), _T_14) @[Mux.scala 81:61]
        node _T_33 = mux(_T_32, _T_19, _T_31) @[Mux.scala 81:58]
        node _T_34 = eq(UInt<3>("h5"), _T_14) @[Mux.scala 81:61]
        node _T_35 = mux(_T_34, _T_22, _T_33) @[Mux.scala 81:58]
        node _T_36 = eq(UInt<3>("h6"), _T_14) @[Mux.scala 81:61]
        node _T_37 = mux(_T_36, _T_25, _T_35) @[Mux.scala 81:58]
        wire _add_WIRE : SInt<32> @[BetterBooth.scala 36:32]
        node _add_T = asUInt(_T_37) @[BetterBooth.scala 36:32]
        node _add_T_1 = asSInt(_add_T) @[BetterBooth.scala 36:32]
        _add_WIRE <= _add_T_1 @[BetterBooth.scala 36:32]
        node _add_T_2 = dshl(cnt, UInt<1>("h1")) @[BetterBooth.scala 36:62]
        node add = dshl(_add_WIRE, _add_T_2) @[BetterBooth.scala 36:54]
        node _sumReg_T = add(sumReg, add) @[BetterBooth.scala 37:22]
        node _sumReg_T_1 = tail(_sumReg_T, 1) @[BetterBooth.scala 37:22]
        node _sumReg_T_2 = asSInt(_sumReg_T_1) @[BetterBooth.scala 37:22]
        sumReg <= _sumReg_T_2 @[BetterBooth.scala 37:12]
        node _yReg_T_7 = dshr(yReg, UInt<2>("h2")) @[BetterBooth.scala 38:18]
        yReg <= _yReg_T_7 @[BetterBooth.scala 38:10]
        node _T_38 = asUInt(sumReg) @[BetterBooth.scala 43:14]
        node _T_39 = bits(reset, 0, 0) @[BetterBooth.scala 39:11]
        node _T_40 = eq(_T_39, UInt<1>("h0")) @[BetterBooth.scala 39:11]
        when _T_40 : @[BetterBooth.scala 39:11]
          printf(clock, UInt<1>("h1"), "yRegExtra = %b, addValue = %b, sum = %b\n", yReg, add, _T_38) : printf_1 @[BetterBooth.scala 39:11]
        node _cnt_T = add(cnt, UInt<1>("h1")) @[BetterBooth.scala 83:18]
        node _cnt_T_1 = tail(_cnt_T, 1) @[BetterBooth.scala 83:18]
        cnt <= _cnt_T_1 @[BetterBooth.scala 83:11]
        io.busy <= UInt<1>("h1") @[BetterBooth.scala 84:15]
      else :
        node _T_41 = eq(UInt<2>("h2"), state) @[BetterBooth.scala 49:17]
        when _T_41 : @[BetterBooth.scala 49:17]
          cnt <= UInt<1>("h0") @[BetterBooth.scala 87:11]
          node result = asUInt(sumReg) @[BetterBooth.scala 88:27]
          io.z <= result @[BetterBooth.scala 89:12]
          node _T_42 = bits(reset, 0, 0) @[BetterBooth.scala 90:13]
          node _T_43 = eq(_T_42, UInt<1>("h0")) @[BetterBooth.scala 90:13]
          when _T_43 : @[BetterBooth.scala 90:13]
            printf(clock, UInt<1>("h1"), "result = %b\n", result) : printf_2 @[BetterBooth.scala 90:13]
          lastResultReg <= result @[BetterBooth.scala 91:21]

